1. Field of the Invention
The present invention relates to a method for fabricating a pixel structure. More particularly, the present invention relates to a method for fabricating a pixel structure with reduced number of photolithography and etching processes (PEPs).
2. Description of Related Art
Displays are communication interfaces between human and information, while flat panel displays are the current trend. The flat panel displays may be divided into the following categories: organic electroluiminescence displays, plasma display panels (PDPs), and TFT-LCDs, and so on. Low-temperature poly-Si TFT LCDs, advantageous in thin thickness, light weight, preferable resolution, are particularly applicable to portable electronic products requiring lightweight and power saving function.
The method for fabricating pixels having the low-temperature poly-Si TFT is complex. Generally speaking, a poly-Si layer and a first capacitor electrode are first formed on a substrate. Then, a channel region, a source region, and a drain region are defined on the poly-Si layer through an ion doping process. After that, a gate dielectric layer is formed to cover the poly-Si layer and the first capacitor electrode. Next, a gate is formed on the gate dielectric layer above the channel region of the poly-Si layer. Then, a dielectric layer is formed to cover the gate and a gate insulating layer, and a contact hole is formed in dielectric layer to expose the source region and the drain region. Afterwards, a source and a drain respectively electrically connected to the source region and the drain region via the contact holes are formed. Then, a passivation layer is formed to cover the source, the drain, and the dielectric layer, in which the passivation layer has a contact hole exposing the drain. Thereafter, a pixel electrode electrically connected to the drain via the contact hole is formed.
In view of the above, the conventional method for fabricating the pixel structure having the low-temperature poly-Si TFT mainly includes the following steps. A poly-Si layer and a first capacitor electrode are formed by a first photolithography and etching process. A gate is formed by a second photolithography and etching process. A contact hole is formed in the dielectric layer by a third photolithography and etching process. A source and a drain are formed by a fourth photolithography and etching process. A contact hole is formed in a passivation layer by a fifth photolithography and etching process. A pixel electrode is formed by a sixth photolithography and etching process. Moreover, in the method for fabricating the pixel structure of the low-temperature poly-Si TFT, two or three photolithography and etching processes are required when forming the channel region, the source region, and the drain region by the ion doping. Therefore, the conventional method for fabricating the pixels of the low-temperature poly-Si TFT generally needs about eight or nine photolithography and etching processes, and the steps of this fabricating method are complex and quite time consuming. The complex fabricating steps result in higher probability of defects in the pixels of the poly-Si TFT, and the low production yield. Furthermore, the conventional method for fabricating the pixel having the low-temperature poly-Si TFT adopts more fabricating steps and requires longer fabricating time. Therefore, the total cost of production is added due to the increase of the cost for purchasing machines and equipments and the material cost for production.